Method of forming a highly integrated non-volatile semiconductor memory device

ABSTRACT

The present invention provides a method of forming a gate structure of a floating gate MOS field effect transistor. The method comprises the steps of: forming a conductive layer on a gate insulating film; forming a dummy layer over the conductive layer; selectively forming a resist pattern over the dummy layer; carrying out an anisotropic etching process for patterning the dummy layer and the conductive layer by use of the resist pattern as a mask, thereby to form a gate structure; removing the resist pattern; forming side wall insulation films on side walls of the gate structure; forming an inter-layer insulator so that the gate structure and the side wall insulation films are completely buried within the inter-layer insulator; carrying out a first planarization process for polishing the inter-layer insulator; and carrying out a second planarization process for selectively etching the inter-layer insulator and the side wall insulation films, so that at least a top portion of the dummy layer is etched; removing the dummy layer; carrying out a third planarization process for selectively etching the inter-layer insulator and the side wall insulation films, so that a planarized surface of the inter-layer insulator and the side wall insulation films is leveled to a planarized surface of the conductive layer, wherein the dummy layer has a higher etching selectivity to the inter-layer insulator than nitride.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a method of forming asemiconductor memory device, and more particularly to a method offorming a non-volatile semiconductor memory device having a high densityintegration of size-reduced memory cells having floating gate MOS fieldeffect transistors with an accurately controlled gate length.

[0002]FIG. 1 is a fragmentary circuit diagram illustrative of a partialarray structure of memory cells having floating gate MOS field effecttransistors in the conventional non-volatile semiconductor memorydevice. Each of the memory cells CELL comprises a pair of a storagecapacitor and a floating gate MOS field effect transistor. The memorycell array has a plurality of bit lines BL extending in a firstdirection. The memory cell array also has a plurality of word lines WLextending in a second direction perpendicular to the first direction.The memory cell array comprises a plurality of memory cell columns, eachof which extends along the first direction and between adjacent two ofthe bit lines BL. Since each of the memory cells has the single pair ofthe floating gate MOS field effect transistor and the storage capacitor,each of the memory cell columns has a plurality of the floating gate MOSfield effect transistors. Each of the floating gate MOS field effecttransistors has a source, a drain, a floating gate and a control gate.Sources of the floating gate MOS field effect transistors in the eachmemory cell column are commonly connected to each other through a commonsource line. Drains of the floating gate MOS field effect transistors inthe each memory cell column are also commonly connected to each otherthrough a common drain line. This common drain line is further connectedthrough a drain selecting transistor SWD to the corresponding bit lineBL. The drain selecting transistor SWD has a gate connected to a drainselector line DSEL, so that the common drain line is made connected tothe bit line BL in accordance with a drain selecting signal transmittedon the drain selector line DSEL connected to the gate of the drainselecting transistor SWD. A source line SL is further provided whichextends in the second direction. The above common source line isconnected through a source selecting transistor SWS to the source lineSL. The source selecting transistor SWS has a gate connected to a sourceselector line SSEL, so that the common source line is made connected tothe source line SL in accordance with a source selecting signaltransmitted on the source selector line SSEL connected to the gate ofthe source selecting transistor SWS. Each of the memory cell rowscomprises the plural floating gate MOS field effect transistors havingcontrol gate electrodes connected to the corresponding word line WL. Theabove circuit configuration forms an AND-type memory. In accordance withthe AND-type memory, it is necessary that the sources and drains of thefloating gate MOS field effect transistors on the memory cell columnTCELLm are separated from the sources and drains of the floating gateMOS field effect transistors on the adjacent memory cell column TCELLn.It is necessary that the control gate electrodes serving as the wordline extend in the gate length direction. By contrast to the AND-typememory, a NOR-type memory has a different structure that the sourceregions of the floating gate MOS field effect transistors on the eachmemory cell column are common to each other, whilst the drain regionsthereof serve as the bit line. A contact is provided for every one orplural memory cells. For these reasons, the control gates of thefloating gate MOS field effect transistors extend in the gate widthdirection. Since as described above, the AND-type memory has thestructure that the control gate electrodes serving as the word lineextend in the gate length direction, it is impossible that after thecontrol gate and the floating gate have been formed, then the source anddrain region are formed. It is necessary for the AND-type memory thatthe floating gate is firstly formed and then the source and drainregions are secondly formed before the control gate is finally formed.

[0003]FIGS. 2A through 2E are fragmentary cross sectional elevationviews illustrative of the first conventional method of forming thefloating gate MOS field effect transistor included in the AND-typememory. This first conventional method is the applicant's admitted priorart.

[0004] With reference to FIG. 2A, shallow trench isolations 202 areselectively formed in an upper region of a p-type silicon substrate 201thereby to define a memory cell formation region 220 in the upper regionof a p-type silicon substrate 201, wherein the memory cell formationregion 220 is surrounded by the trench isolations 202. A tunnel gateinsulation film 205 is formed on the memory cell formation region 220. Afirst polycrystalline silicon film 206 is formed on the tunnel gateinsulation film 205. A first silicon oxide film 221 is formed on thefirst polycrystalline silicon film 206. A first silicon nitride film 222is formed on the first silicon oxide film 221. An antireflective film223 is formed on the first silicon nitride film 222 to form multilayerlaminations. A resist pattern 224 is formed on the antireflective film223. An anisotropic etching process is carried out by use of the resistpattern 224 as a mask to pattern the multilayer laminations therebyforming a gate structure 225, which comprises the tunnel gate insulationfilm 205, the first polycrystalline silicon film 206, the first siliconoxide film 221, the first silicon nitride film 222 and theantireflective film 223. The used resist pattern 224 is removed.

[0005] With reference to FIG. 2B, a first ion-implantation process iscarried out by use of the gate structure 225 as a mask for introducingan n-type impurity into selected upper regions of the memory cellformation region 220 except under the gate structure 225 thereby toselectively form n⁻-type lightly doped diffusion regions 204 in theselected upper regions of the memory cell formation region 220 exceptunder the gate structure 225, wherein the n⁻-type lightly dopeddiffusion regions 204 are defined by the shallow trench isolationregions 202 and are self-aligned to the gate structure 225. An oxidefilm is entirely formed which extends over the shallow trench isolationregions 202, the n⁻-type lightly doped diffusion regions 204 and sidewalls and a top surface of the gate structure 225. An anisotropicetching process is then carried out to the oxide film so as toselectively leave the oxide film on the side walls of the gate structure225, whereby side wall oxide films 209 are formed on the side walls ofthe gate structure 225. A second ion-implantation process is carried outby use of the gate structure 225 and the side wall oxide films 209 as amask for introducing an n-type impurity into selected upper regions ofthe memory cell formation region 220 except under the gate structure 225and the side wall oxide films 209 thereby to selectively form n⁺-typesource and drain regions 203S and 203D in the selected upper regions ofthe memory cell formation region 220 except under the gate structure 225and the side wall oxide films 209, wherein the n⁺-type source and drainregions 203S and 203D are defined by the shallow trench isolationregions 202 and are self-aligned to the side wall oxide films 209. As aresult, the n⁻-type lightly doped diffusion regions 204 remain under theside wall oxide films 209. The boundaries between the n⁺-type source anddrain regions 203S and 203D and the n⁻-type lightly doped diffusionregions 204 are aligned to the outside edges of the side wall oxidefilms 209.

[0006] With reference to FIG. 2C, a first inter-layer insulator 210 isentirely formed over the shallow trench isolation regions 202, then⁺-type source and drain regions 203S and 203D, the side wall oxidefilms 209 and the gate structure 225, whereby the side wall oxide films209 and the gate structure 225 are completely buried within the firstinter-layer insulator 210. The first inter-layer insulator 210 comprisea boro-phospho-silicate glass film. A planarization process is carriedout to the first inter-layer insulator 210 and the gate structure 225 bya chemical mechanical polishing process, whereby upper regions of thefirst inter-layer insulator 210 and the gate structure 225 with the sidewall oxide films 209 are removed, wherein the silicon nitride film 222serves as a polishing stopper. The chemical mechanical polishing processis stopped soon after the top surface of the silicon nitride film 222 isshown. Namely, a planarized surface is formed, wherein a planarized topsurface of the first inter-layer insulator 210 is leveled to theplanarized top surface of the silicon nitride film 222 of the gatestructure 225 and also leveled to the planarized top surface of the sidewall oxide films 209. The silicon nitride film 222 is much slower inetching rate than the first inter-layer insulator 210, whereby thesilicon nitride film 222 is sufficient in serving as the polishingstopper in the chemical mechanical polishing process, thereby preventingthe first polycrystalline silicon film 206 from being polished.

[0007] With reference to FIG. 2D, the silicon nitride film 222 isremoved. Further, the first inter-layer insulator 210 and the side walloxide films 209 are selectively etched to the same level as the topsurface of the first polycrystalline silicon film 206 of the gatestructure 225. At the same time, the silicon oxide film 221 is alsoremoved. As a result, an almost planarized surface is formed, whereinthe a planarized top surface of the first inter-layer insulator 210 isleveled to the planarized top surface of the first polycrystallinesilicon film 206.

[0008] With reference to FIG. 2E, a second polycrystalline silicon film207 is entirely formed over the planarized top surfaces of the firstinter-layer insulator 210, the side wall oxide films 209 and the firstpolycrystalline silicon film 206. The second polycrystalline siliconfilm 207 is then patterned to form a second polycrystalline siliconpattern 207. The second polycrystalline silicon pattern 207 has a widthsufficiently covering the first polycrystalline silicon film 206. Thesecond polycrystalline silicon pattern 207 extends along the columndirection perpendicular to the width direction. An ONO inter-gateinsulator 208 is entirely formed on the second polycrystalline siliconpattern 207 and the first inter-layer insulator 210. The ONO inter-gateinsulator 208 comprises laminations of an oxide film, a nitride film andan oxide film. A third polycrystalline silicon film 211 is entirelyformed on the ONO inter-gate insulator 208. Laminations of the thirdpolycrystalline silicon film 211, the ONO inter-gate insulator 208, thesecond polycrystalline silicon pattern 207 and the first polycrystallinesilicon film 206 are selectively etched or patterned to have thelaminations extend in the row direction. The third polycrystallinesilicon film 211 forms a control gate electrode as a word line. Thefirst polycrystalline silicon film 206 and the second polycrystallinesilicon pattern 207 form a floating gate electrode. As a result, thefloating gate MOS field effect transistor is completed.

[0009] As described above, the conventional method utilizes the nitridefilm 222 which serves as a polishing stopper in the chemical mechanicalpolishing process, wherein the nitride film 222 is much larger inpolishing selectivity than the first polycrystalline silicon film 206and the first inter-layer insulator 210 of boro-phospho-silicate glass.Namely, the nitride film 222 is used as a dummy film. On the other hand,the resist film 224 is used for shaping the gate structure 225. Thenitride film 222 has an etching selectivity of about 0.56 to the resistfilm 224. Namely, the nitride film 222 is lower in etching selectivitythan the resist film 224. This means it difficult to form the nitridefilm 222 in highly accurate dimension or in highly accurate width. Theresist film 224 overlying the antireflective layer 223 is used as a maskfor selectively etching the antireflective layer 223, the nitride film222, the silicon oxide film 221 and the first polycrystalline siliconfilm 206. The nitride film 222 is lower in etching selectivity than theresist film 224. Namely, the nitride film 222 is lower in etching ratethan the resist film 224, for which reason opposite side edges of theresist film 224 are over-etched, whereby a horizontal size of the resistfilm 224 is reduced from the designed size, before the above gatestructure 225 is completely defined by this etching process. Theover-etched and size-reduced resist film 224 causes the nitride film 222to be also over-etched in horizontal direction and to be reduced inhorizontal size, whereby the nitride film 222 gradually varies inhorizontal size, so that the horizontal size of the nitride film 222 isgradually reduced upwardly. Namely, the side walls of the nitride film222 are not vertical rather sloped. The cross sectional vertical shapeof the nitride film 222 is trapezoid. The over-etched and size-reducedresist film 224 further causes the silicon oxide film 221 and the firstpolycrystalline silicon film 206 to be also over-etched in horizontaldirection and to be reduced in horizontal size. The above horizontalsize reductions of the nitride film 222, the silicon oxide film 221 andthe first polycrystalline silicon film 206 means that the gate structure225 is reduced in horizontal size. This means that the gate structure225 is reduced in size in the gate length direction. The n⁻-type lightlydoped diffusion regions 204 are self-aligned to the edges of the gatestructure 225. The reduction in size in the gate length direction of thegate structure 225 causes variation in position of the inner edges ofthe n⁻-type lightly doped diffusion regions 204, whereby a channellength defined between the inner edges of the n⁻-type lightly dopeddiffusion regions 204 is reduced. This variation in channel lengthcauses variations in characteristics and performances of the memorycells, for example, the necessary times of writing and erasing data, andON-current for reading out data. This makes it difficult to realizeadvanced memory cells having 0.22 micrometers gate length.

[0010] In the above circumstances, it had been required to develop anovel method of forming a non-volatile semiconductor memory device freefrom the above problem.

SUMMARY OF THE INVENTION

[0011] Accordingly, it is an object of the present invention to providea novel method of forming a non-volatile semiconductor memory devicefree from the above problems.

[0012] It is a further object of the present invention to provide anovel method of forming a non-volatile semiconductor memory device freefrom any substantive variation in channel length.

[0013] It is a still further object of the present invention to providea novel method of forming a non-volatile semiconductor memory devicebeing highly reliable in characteristics and performances.

[0014] It is yet a further object of the present invention to provide anovel method of forming a non-volatile semiconductor memory device freefrom any substantive variations in the necessary times of writing anderasing data, and in ON-current for reading out data.

[0015] It is another object of the present invention to provide a novelmethod of forming a gate structure of a floating gate MOS field effecttransistor for a semiconductor memory device free from the aboveproblems.

[0016] It is further another object of the present invention to providea novel method of forming a gate structure of a floating gate MOS fieldeffect transistor for a semiconductor memory device free from anysubstantive variation in channel length.

[0017] It is still further another object of the present invention toprovide a novel method of forming a gate structure of a floating gateMOS field effect transistor for a semiconductor memory device beinghighly reliable in characteristics and performances.

[0018] It is yet further another object of the present invention toprovide a novel method of forming a gate structure of a floating gateMOS field effect transistor for a semiconductor memory device free fromany substantive variations in the necessary times of writing and erasingdata, and in ON-current for reading out data.

[0019] The first present invention provides a method of patterning aconductive layer buried in an inter-layer insulator. The methodcomprises the steps of: forming a dummy layer over a conductive layer;selectively forming a resist pattern over the dummy layer; carrying outan anisotropic etching process for patterning the dummy layer and theconductive layer by use of the resist pattern as a mask; removing theresist pattern; forming an inter-layer insulator so that the dummy layerand the conductive layer are completely buried within the inter-layerinsulator; carrying out a first planarization process for polishing theinter-layer insulator; and carrying out a second planarization processfor selectively etching the inter-layer insulator, so that at least atop portion of the dummy layer is etched; removing the dummy layer;carrying out a third planarization process for selectively etching theinter-layer insulator, so that a planarized surface of the inter-layerinsulator is leveled to a planarized surface of the conductive layer,wherein the dummy layer has a higher etching selectivity to theinter-layer insulator than nitride.

[0020] The second present invention provides a method of forming a gatestructure of a floating gate MOS field effect transistor. The methodcomprises the steps of: forming a conductive layer on a gate insulatingfilm; forming a dummy layer over the conductive layer; selectivelyforming a resist pattern over the dummy layer; carrying out ananisotropic etching process for patterning the dummy layer and theconductive layer by use of the resist pattern as a mask, thereby to forma gate structure; removing the resist pattern; forming side wallinsulation films on side walls of the gate structure; forming aninter-layer insulator so that the gate structure and the side wallinsulation films are completely buried within the inter-layer insulator;carrying out a first planarization process for polishing the inter-layerinsulator; and carrying out a second planarization process forselectively etching the inter-layer insulator and the side wallinsulation films, so that at least a top portion of the dummy layer isetched; removing the dummy layer; carrying out a third planarizationprocess for selectively etching the inter-layer insulator and the sidewall insulation films, so that a planarized surface of the inter-layerinsulator and the side wall insulation films is leveled to a planarizedsurface of the conductive layer, wherein the dummy layer has a higheretching selectivity to the inter-layer insulator than nitride.

[0021] The third present invention provides a dummy layer patternprovided over a conductive layer pattern buried in an inter-layerinsulator for protecting the conductive layer pattern from beingover-polished by a chemical mechanical polishing process, wherein thedummy layer pattern has a higher etching selectivity to the inter-layerinsulator than nitride.

[0022] The above and other objects, features and advantages of thepresent invention will be apparent from the following descriptions.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Preferred embodiments according to the present invention will bedescribed in detail with reference to the accompanying drawings.

[0024]FIG. 1 is a fragmentary circuit diagram illustrative of a partialarray structure of memory cells having floating gate MOS field effecttransistors in the conventional non-volatile semiconductor memorydevice. Each of the memory cells CELL comprises a pair of a storagecapacitor and a floating gate MOS field effect transistor.

[0025]FIGS. 2A through 2E are fragmentary cross sectional elevationviews illustrative of the first conventional method of forming thefloating gate MOS field effect transistor included in the AND-typememory. This first conventional method is the applicant's admitted priorart.

[0026]FIG. 3A is a fragmentary plane view illustrative of asemiconductor memory device having an AND-type memory cell structure ina first preferred embodiment in accordance with the present invention.

[0027]FIG. 3B is a fragmentary cross sectional elevation view takenalong an A-A line of FIG. 3 illustrative of a semiconductor memorydevice having an AND-type memory cell structure in a first preferredembodiment in accordance with the present invention.

[0028]FIG. 3C is a fragmentary cross sectional elevation view takenalong a B-B line of FIG. 3 illustrative of a semiconductor memory devicehaving an AND-type memory cell structure in a first preferred embodimentin accordance with the present invention.

[0029]FIG. 4 is a fragmentary perspective view illustrative of asemiconductor memory device having an AND-type memory cell structure ina first preferred embodiment in accordance with the present invention.

[0030]FIGS. 5A through 5L are fragmentary cross sectional elevationviews illustrative of floating gate MOS field effect transistors in eachof semiconductor memory cells in sequential fabrication steps involvedin the novel fabrication method in the first preferred embodiment inaccordance with the present invention.

[0031]FIG. 6 is a fragmentary cross sectional elevation viewillustrative of a semiconductor device having a memory cell area and aperipheral circuit area.

DISCLOSURE OF THE INVENTION

[0032] The first present invention provides a method of patterning aconductive layer buried in an inter-layer insulator. The methodcomprises the steps of: forming a dummy layer over a conductive layer;selectively forming a resist pattern over the dummy layer; carrying outan anisotropic etching process for patterning the dummy layer and theconductive layer by use of the resist pattern as a mask; removing theresist pattern; forming an inter-layer insulator so that the dummy layerand the conductive layer are completely buried within the inter-layerinsulator; carrying out a first planarization process for polishing theinter-layer insulator; and carrying out a second planarization processfor selectively etching the inter-layer insulator, so that at least atop portion of the dummy layer is etched removing the dummy layer;carrying out a third planarization process for selectively etching theinter-layer insulator, so that a planarized surface of the inter-layerinsulator is leveled to a planarized surface of the conductive layer,wherein the dummy layer has a higher etching selectivity to theinter-layer insulator than nitride.

[0033] In accordance with the first present invention, the dummy layerwhich serves as a polishing stopper in the chemical mechanical polishingprocess has a higher etching selectivity to the inter-layer insulatorthan nitride. The resist film is used for shaping the gate structure.The dummy layer has a higher etching selectivity to the resist film thanabout 0.56. Namely, the dummy layer is higher in etching selectivitythan the nitride film used in the conventional method. This means itpossible to form the dummy layer in highly accurate dimension or inhighly accurate width. The resist film overlying the dummy layer is usedas a mask for selectively etching the dummy layer and the conductivefilm. The dummy layer is not so lower in etching selectivity than theresist film. Namely, the dummy layer is not so lower in etching ratethan the resist film, for which reason opposite side edges of the resistfilm are not over-etched, whereby a horizontal size of the resist filmremains unchanged at the designed size, even after the above gatestructure is completely defined by the etching process. Theover-etching-free and size-reduction-free resist film causes the dummylayer to be free of any over-etching in horizontal direction and toremain unchanged in horizontal size, whereby the dummy layer remainsunchanged in horizontal size, so that the horizontal size of the dummylayer remains unchanged in the vertical direction or the thicknessdirection. Namely, the side walls of the dummy layer are vertical. Thecross sectional vertical shape of the dummy layer is rectangle. Theover-etching-free and size-reduction-free resist film further causes theconductive layer to be also free from any over-etching in horizontaldirection and to remain unchanged in horizontal size. The abovehorizontal size unchanges of the dummy layer and the conductive layermeans that the gate structure remains unchanged in horizontal size. Thismeans that the gate structure remains unchanged in size in the gatelength direction. Lightly doped diffusion regions are self-aligned tothe edges of the gate structure. No variation in size in the gate lengthdirection of the gate structure causes no variation in position of theinner edges of the lightly doped diffusion regions, whereby a channellength defined between the inner edges of the lightly doped diffusionregions is reduced. No variation in channel length causes no variationsin characteristics and performances of the memory cells, for example,the necessary times of writing and erasing data, and ON-current forreading out data. This makes it possible to realize advanced memorycells having 0.22 micrometers gate length.

[0034] It is possible that the dummy layer comprises an amorphoussilicon layer.

[0035] It is also possible that the dummy layer comprises apolycrystalline silicon layer.

[0036] It is also possible that the dummy layer comprises a CVD oxidelayer.

[0037] It is also possible that the dummy layer comprises a plasmaenhanced silicon oxide layer.

[0038] It is also possible that the dummy layer comprises aboro-phospho-silicate glass layer.

[0039] It is also possible that the second and third planarizationprocesses are plasma etching processes.

[0040] It is also possible that the second and third planarizationprocesses are wet etching processes.

[0041] It is also possible that the first planarization process is achemical mechanical polishing process.

[0042] It is also possible that the dummy layer is removed by a dryetching process.

[0043] It is also possible that the conductive layer comprises animpurity-doped polycrystalline silicon layer.

[0044] It is also possible to further comprise the step of: forming asilicon oxide film on the polycrystalline silicon layer before the dummylayer is formed on the silicon oxide film and over the polycrystallinesilicon layer.

[0045] It is also possible to further comprise the step of: forming anantireflective layer on the dummy layer before the resist film isselectively formed on the antireflective layer and over the dummy layer.

[0046] It is also possible that the first inter-layer insulatorcomprises a boro-phospho-silicate glass film.

[0047] It is also possible that the dummy layer and the conductive layeras patterned have a width of not more than about 0.22 micrometers.

[0048] The second present invention provides a method of forming a gatestructure of a floating gate MOS field effect transistor. The methodcomprises the steps of: forming a conductive layer on a gate insulatingfilm; forming a dummy layer over the conductive layer; selectivelyforming a resist pattern over the dummy layer; carrying out ananisotropic etching process for patterning the dummy layer and theconductive layer by use of the resist pattern as a mask, thereby to forma gate structure removing the resist pattern; forming side wallinsulation films on side walls of the gate structure; forming aninter-layer insulator so that the gate structure and the side wallinsulation films are completely buried within the inter-layer insulator;carrying out a first planarization process for polishing the inter-layerinsulator; and carrying out a second planarization process forselectively etching the inter-layer insulator and the side wallinsulation films, so that at least a top portion of the dummy layer isetched; removing the dummy layer; carrying out a third planarizationprocess for selectively etching the inter-layer insulator and the sidewall insulation films, so that a planarized surface of the inter-layerinsulator and the side wall insulation films is leveled to a planarizedsurface of the conductive layer, wherein the dummy layer has a higheretching selectivity to the inter-layer insulator than nitride.

[0049] In accordance with the second present invention, the dummy layerwhich serves as a polishing stopper in the chemical mechanical polishingprocess has a higher etching selectivity to the inter-layer insulatorthan nitride. The resist film is used for shaping the gate structure.The dummy layer has a higher etching selectivity to the resist film thanabout 0.56. Namely, the dummy layer is higher in etching selectivitythan the nitride film used in the conventional method. This means itpossible to form the dummy layer in highly accurate dimension or inhighly accurate width. The resist film overlying the dummy layer is usedas a mask for selectively etching the dummy layer and the conductivefilm. The dummy layer is not so lower in etching selectivity than theresist film. Namely, the dummy layer is not so lower in etching ratethan the resist film, for which reason opposite side edges of the resistfilm are not over-etched, whereby a horizontal size of the resist filmremains unchanged at the designed size, even after the above gatestructure is completely defined by the etching process. Theover-etching-free and size-reduction-free resist film causes the dummylayer to be free of any over-etching in horizontal direction and toremain unchanged in horizontal size, whereby the dummy layer remainsunchanged in horizontal size, so that the horizontal size of the dummylayer remains unchanged in the vertical direction or the thicknessdirection. Namely, the side walls of the dummy layer are vertical. Thecross sectional vertical shape of the dummy layer is rectangle. Theover-etching-free and size-reduction-free resist film further causes theconductive layer to be also free from any over-etching in horizontaldirection and to remain unchanged in horizontal size. The abovehorizontal size unchanges of the dummy layer and the conductive layermeans that the gate structure remains unchanged in horizontal size. Thismeans that the gate structure remains unchanged in size in the gatelength direction. Lightly doped diffusion regions are self-aligned tothe edges of the gate structure. No variation in size in the gate lengthdirection of the gate structure causes no variation in position of theinner edges of the lightly doped diffusion regions, whereby a channellength defined between the inner edges of the lightly doped diffusionregions is reduced. No variation in channel length causes no variationsin characteristics and performances of the memory cells, for example,the necessary times of writing and erasing data, and ON-current forreading out data. This makes it possible to realize advanced memorycells having 0.22 micrometers gate length.

[0050] It is preferable that the dummy layer comprises an amorphoussilicon layer.

[0051] It is also preferable that the dummy layer comprises apolycrystalline silicon layer.

[0052] It is also preferable that the dummy layer comprises a CVD oxidelayer.

[0053] It is also preferable that the dummy layer comprises a plasmaenhanced silicon oxide layer.

[0054] It is also preferable that the dummy layer comprises aboro-phospho-silicate glass layer.

[0055] It is also preferable that the second and third planarizationprocesses are plasma etching processes.

[0056] It is also preferable that the second and third planarizationprocesses are wet etching processes.

[0057] It is also preferable that the first planarization process is achemical mechanical polishing process.

[0058] It is also preferable that the dummy layer is removed by a dryetching process.

[0059] It is also preferable that the conductive layer comprises animpurity-doped polycrystalline silicon layer.

[0060] It is also preferable to further comprise the step of: forming asilicon oxide film on the polycrystalline silicon layer before the dummylayer is formed on the silicon oxide film and over the polycrystallinesilicon layer.

[0061] It is also preferable to further comprise the step of: forming anantireflective layer on the dummy layer before the resist film isselectively formed on the antireflective layer and over the dummy layer.

[0062] It is also preferable that the first inter-layer insulatorcomprises a boro-phospho-silicate glass film.

[0063] It is also preferable that the dummy layer and the conductivelayer as patterned have a width of not more than about 0.22 micrometers.

[0064] It is also preferable to further comprise the steps of:selectively forming a capacitive conductive film extending on at leastan entire top surface region of the conductive layer, so that thecapacitive conductive film and the conductive layer forms a floatinggate electrode; forming an inter-gate insulation film over thecapacitive conductive film; forming a second conductive film over thecapacitive insulation film, wherein the second conductive film forms acontrol gate electrode.

[0065] The third present invention provides a dummy layer patternprovided over a conductive layer pattern buried in an inter-layerinsulator for protecting the conductive layer pattern from beingover-polished by a chemical mechanical polishing process, wherein thedummy layer pattern has a higher etching selectivity to the inter-layerinsulator than nitride.

[0066] In accordance with the third present invention, the dummy layerwhich serves as a polishing stopper in the chemical mechanical polishingprocess has a higher etching selectivity to the inter-layer insulatorthan nitride. The resist film is used for shaping the gate structure.The dummy layer has a higher etching selectivity to the resist film thanabout 0.56. Namely, the dummy layer is higher in etching selectivitythan the nitride film used in the conventional method. This means itpossible to form the dummy layer in highly accurate dimension or inhighly accurate width. The resist film overlying the dummy layer is usedas a mask for selectively etching the dummy layer and the conductivefilm. The dummy layer is not so lower in etching selectivity than theresist film. Namely, the dummy layer is not so lower in etching ratethan the resist film, for which reason opposite side edges of the resistfilm are not over-etched, whereby a horizontal size of the resist filmremains unchanged at the designed size, even after the above gatestructure is completely defined by the etching process. Theover-etching-free and size-reduction-free resist film causes the dummylayer to be free of any over-etching in horizontal direction and toremain unchanged in horizontal size, whereby the dummy layer remainsunchanged in horizontal size, so that the horizontal size of the dummylayer remains unchanged in the vertical direction or the thicknessdirection. Namely, the side walls of the dummy layer are vertical. Thecross sectional vertical shape of the dummy layer is rectangle. Theover-etching-free and size-reduction-free resist film further causes theconductive layer to be also free from any over-etching in horizontaldirection and to remain unchanged in horizontal size. The abovehorizontal size unchanges of the dummy layer and the conductive layermeans that the gate structure remains unchanged in horizontal size. Thismeans that the gate structure remains unchanged in size in the gatelength direction. Lightly doped diffusion regions are self-aligned tothe edges of the gate structure. No variation in size in the gate lengthdirection of the gate structure causes no variation in position of theinner edges of the lightly doped diffusion regions, whereby a channellength defined between the inner edges of the lightly doped diffusionregions is reduced. No variation in channel length causes no variationsin characteristics and performances of the memory cells, for example,the necessary times of writing and erasing data, and ON-current forreading out data. This makes it possible to realize advanced memorycells having 0.22 micrometers gate length.

[0067] It is preferable that the dummy layer pattern comprises anamorphous silicon layer.

[0068] It is also preferable that the dummy layer pattern comprises apolycrystalline silicon layer.

[0069] It is also preferable that the dummy layer pattern comprises aCVD oxide layer.

[0070] It is also preferable that the dummy layer dummy layer pattern aplasma enhanced silicon oxide layer.

[0071] It is also preferable that the dummy layer dummy layer pattern aboro-phospho-silicate glass layer.

[0072] Preferred Embodiment

[0073] A first embodiment according to the present invention will bedescribed in detail with reference to the drawings. FIG. 3A is afragmentary plane view illustrative of a semiconductor memory devicehaving an AND-type memory cell structure in a first preferred embodimentin accordance with the present invention. FIG. 3B is a fragmentary crosssectional elevation view taken along an A-A line of FIG. 3 illustrativeof a semiconductor memory device having an AND-type memory cellstructure in a first preferred embodiment in accordance with the presentinvention. FIG. 3C is a fragmentary cross sectional elevation view takenalong a B-B line of FIG. 3 illustrative of a semiconductor memory devicehaving an AND-type memory cell structure in a first preferred embodimentin accordance with the present invention. FIG. 4 is a fragmentaryperspective view illustrative of a semiconductor memory device having anAND-type memory cell structure in a first preferred embodiment inaccordance with the present invention.

[0074] The novel semiconductor memory device is formed over a p-typesilicon substrate 101. A plurality of shallow trench isolations STI 102of silicon oxide are formed in selected upper regions of the p-typesilicon substrate 101, wherein the shallow trench isolations STI 102extend in a column direction. A plurality of memory cell formationregions are defined between the shallow trench isolations STI 102. Ineach of the memory cell formation regions, a pair of n-type source anddrain regions 103S and 103D is provided, wherein the n-type source anddrain regions 103S and 103D extend in the column direction and also inparallel to the shallow trench isolations STI 102. Outside edges of then-type source and drain regions 103S and 103D are bounded with theinside edges of the shallow trench isolations STI 102. Lightly-dopeddrain regions 104 are provided which extend from the inside edges of then-type source and drain regions 103S and 103D. The lightly-doped drainregions 104 extend in the column direction and also in parallel to then-type source and drain regions 103S and 103D. A channel region isdefined between the inside edges of the lightly-doped drain regions 104.A tunnel gate insulation film 105 is provided which extends on thechannel region. A polycrystalline silicon floating gate electrode 106 isprovided on the tunnel gate insulation film 105. Side wall insulationfilms 109 are provided on side walls of the laminations ofpolycrystalline silicon floating gate electrode 106 and the tunnel gateinsulation film 105. The side wall insulation films 109 comprise siliconoxide films. The lightly-doped drain regions 104 are positioned underthe side wall insulation films 109. The inside edges of thelightly-doped drain regions 104 are self-aligned to the boundary betweenthe side wall insulation films 109 and the side walls of the laminationsof polycrystalline silicon floating gate electrode 106 and the tunnelgate insulation film 105. A first inter-layer insulator 110 is providedwhich extends over the n-type source and drain regions 103S and 103D andthe shallow trench isolations STI 102. The first inter-layer insulator110 surrounds the side wall insulation films 109 and the side walls ofthe laminations of polycrystalline silicon floating gate electrode 106and the tunnel gate insulation film 105. The first inter-layer insulator110 comprises a boro-phospho-silicate glass film. The first inter-layerinsulator 110 has a planarized top surface which is leveled to theplanarized top surfaces of the side walls of the laminations ofpolycrystalline silicon floating gate electrode 106. The boundarybetween the side wall insulation films 109 and the first inter-layerinsulator 110 are self-aligned to the boundary between the n-type sourceand drain regions 103S and 103D and the lightly-doped drain regions 104.A polycrystalline silicon capacitive layer 107 is provided which extendsover the planarized top surfaces of the first inter-layer insulator 110,the side wall oxide films 109 and the polycrystalline silicon floatinggate electrode 106, so that the outside edges of the polycrystallinesilicon capacitive layer 107 are aligned to the boundaries between then-type source and drain regions 103S and 103D and the shallow trenchisolations 102. The polycrystalline silicon capacitive layer 107 is incontact with the polycrystalline silicon floating gate electrode 106. Aninter-gate insulator 108 is entirely provided on the polycrystallinesilicon capacitive layer 107 and the first inter-layer insulator 110. Aplurality of polycrystalline silicon control gate electrode layers 111are provided which extends on the inter-gate insulator 108. Theplurality of polycrystalline silicon control gate electrode layers 111extend in row direction perpendicular to the column direction. Theplurality of polycrystalline silicon control gate electrode layers 111serve as word lines. A top insulation film 112 is provided on thepolycrystalline silicon control gate electrode layers 111. A pluralityof gate structures 125 are provided over the substrate 101, wherein eachof the gate structures 125 comprises laminations of the tunnel gateinsulation film 105, the polycrystalline silicon floating gate electrode106, the polycrystalline silicon capacitive layer 107, the inter-gateinsulator 108, the polycrystalline silicon control gate electrode layer111 and the top insulation film 112. Each of the gate structures 125extends in the row direction.

[0075] In accordance with the AND-type memory device, the memory cellsare aligned in the memory cell formation region defined between theshallow trench isolation regions, The drain region of the each memorycell is connected through a selective block drain selector gate to a bitline. The source region of the each memory cell is connected through aselective block source selector gate to a source line.

[0076] FIGS. SA through 5L are fragmentary cross sectional elevationviews illustrative of floating gate MOS field effect transistors in eachof semiconductor memory cells in sequential fabrication steps involvedin the novel fabrication method in the first preferred embodiment inaccordance with the present invention.

[0077] With reference to FIG. 5A, shallow trench isolations STI 102 areselectively formed in upper regions of a p-type silicon substrate 101,wherein the shallow trench isolations STI 102 extend in the columndirection. The shallow trench isolations STI 102 may be formed asfollow. A selective etching method is carried out by use of a resistpattern formed over the top surface of the p-type silicon substrate 101,to selectively form shallow trenches in upper regions of the p-typesilicon substrate 101. The shallow trenches extend in the columndirection. A silicon oxide film is entirely deposited so that thesilicon oxide film completely fills the shallow trenches and extendsover the top surface of the p-type silicon substrate 101. A chemicalmechanical polishing process is then carried out for polishing thesilicon oxide film so that the silicon oxide film remains only theshallow trenches, thereby forming the plural shallow trench isolationsSTI 102 extending in the column direction have a row direction size ofabout 0.24 micrometers. The each memory cell formation region 120defined between the adjacent two of the shallow trench isolations STI102 also extends in the column direction and has a row direction size ofabout 0.68 micrometers.

[0078] With reference to FIG. 5B, a tunnel gate insulation film 105 ofsilicon oxide is formed by a thermal oxidation on the each memory cellformation region 120. The tunnel gate insulation film 105 has athickness of 90 angstroms. A polycrystalline silicon floating gateelectrode layer 106 is formed on the tunnel gate insulation film 105.The polycrystalline silicon floating gate electrode layer 106 has athickness of 1000 angstroms. A silicon oxide film 121 is formed on thepolycrystalline silicon floating gate electrode layer 106. The siliconoxide film 121 has a thickness of 250 angstroms. An amorphous silicondummy layer 122 is formed on the silicon oxide film 121. The amorphoussilicon dummy layer 122 has a thickness of 2000 angstroms. The amorphoussilicon dummy layer 122 serves as a dummy layer in the later process ofchemical mechanical polishing. An anti-reflective layer 123 is formed onthe amorphous silicon dummy layer 122. The anti-reflective layer 123 hasa thickness in the range of 100-350 angstroms. A resist pattern 124 isselectively formed on the anti-reflective layer 123. An anisotropicetching process is carried out by use of the resist pattern 124 as amask for selectively etching laminations of the anti-reflective layer123, the amorphous silicon dummy layer 122, the silicon oxide film 121,the polycrystalline silicon floating gate electrode layer 106 and thetunnel gate insulation film 105, thereby to form a gate structure 125which comprises the patterned laminations of the anti-reflective layer123, the amorphous silicon dummy layer 122, the silicon oxide film 121,the polycrystalline silicon floating gate electrode layer 106 and thetunnel gate insulation film 105. The gate structure 125 has a rowdirection size of about 0.22 micrometers. The gate structure 125 extendsin the column direction. The gate structure 125 extends on the selectedregion of the memory cell formation region 120 defined between theadjacent two of the shallow trench isolations 102. The above selectiveanisotropic etching process is the plasma etching process. For etchingthe anti-reflective layer 123, CF4 gas is used. For the amorphoussilicon dummy layer 122, Cl2+HBr gas is used. For both the silicon oxidefilm 121 and the tunnel gate insulation film 105, CF4 gas is used. Forthe polycrystalline silicon floating gate electrode layer 106, Cl2+HBrgas is used. The etching selectivity of the amorphous silicon dummylayer 122 to the resist pattern 124 is in the range of 1-2. The etchingselectivity of the nitride layer to the resist pattern 124 is 0.56.Namely, the amorphous silicon dummy layer 122 is larger in etchingselectivity to the resist pattern 124 than the nitride layer, for whichreason opposite side edges of the resist film 124 are not over-etched,whereby a horizontal size of the resist film 124 remains unchanged fromthe designed size, even after the above gate structure 125 is completelydefined by this etching process. The over-etching-free andsize-reduction-free resist film 124 makes the amorphous silicon dummylayer 122 free from any over-etching in horizontal direction and remainunchanged in horizontal size, whereby the amorphous silicon dummy layer122 remains unchanged in horizontal size, so that the horizontal size ofthe amorphous silicon dummy layer 122 is constant in the verticaldirection or the thickness direction. Namely, the side walls of theamorphous silicon dummy layer 122 are just vertical. The cross sectionalvertical shape of the amorphous silicon dummy layer 122 is rectangle.The over-etching-free and size-reduction-free resist film 124 furthercauses the silicon oxide film 121 and the polycrystalline siliconfloating gate electrode layer 106 to be free from any over-etching inhorizontal direction and to remain unchanged in horizontal size. Theabove horizontal size unchanges of the amorphous silicon dummy layer122, the silicon oxide film 121 and the polycrystalline silicon floatinggate electrode layer 106 means that the gate structure 125 remainsunchanged in horizontal size. This means that the gate structure 125 isreduced in size in the gate length direction.

[0079] With reference to FIG. 5C, the used resist pattern 124 isremoved. A first ion-implantation process is carried out by use of thegate structure 125 as a mask for selectively introducing an n-typeimpurity such as arsenic at a low impurity concentration of 3E13/cm²into selected upper regions of the memory cell formation region 120except under the gate structure 125 thereby to selectively form n⁻-typelightly doped diffusion regions 104 in the selected upper regions of thememory cell formation region 120 except under the gate structure 125,wherein the n⁻-type lightly doped diffusion regions 104 are defined bythe shallow french isolation regions 102 and are self-aligned to thegate structure 125.

[0080] With reference to FIG. 5D, an oxide film is entirely formed whichextends over the shallow trench isolation regions 102, the n⁻-typelightly doped diffusion regions 104 and side walls and a top surface ofthe gate structure 125 by a chemical vapor deposition method. Ananisotropic etching process is then carried out to the oxide film so asto selectively leave the oxide film on the side walls of the gatestructure 125, whereby side wall oxide films 109 are formed on the sidewalls of the gate structure 125. A second ion-implantation process iscarried out by use of the gate structure 125 and the side wall oxidefilms 109 as a mask for introducing an n-type impurity such as arsenicinto selected upper regions of the memory cell formation region 120except under the gate structure 125 and the side wall oxide films 109 ata high impurity concentration of 4E15/cm2 thereby to selectively formn⁺-type source and drain regions 103S and 103D in the selected upperregions of the memory cell formation region 120 except under the gatestructure 125 and the side wall oxide films 109, wherein the n⁺-typesource and drain regions 103S and 103D are defined by the shallow trenchisolation regions 102 and are self-aligned to the side wall oxide films109. As a result, the n⁻-type lightly doped diffusion regions 104 remainunder the side wall oxide films 109. The boundaries between the n⁺-typesource and drain regions 103S and 103D and the n⁻-type lightly dopeddiffusion regions 104 are aligned to the outside edges of the side walloxide films 109.

[0081] With reference to FIG. 5E, a first inter-layer insulator 110having a thickness of 6000 angstroms is entirely formed over the shallowtrench isolation regions 102, the n⁺-type source and drain regions 103Sand 103D, the side wall oxide films 109 and the gate structure 125 by achemical vapor deposition, whereby the side wall oxide films 109 and thegate structure 125 are completely buried within the first inter-layerinsulator 110. The first inter-layer insulator 110 comprise aboro-phospho-silicate glass film.

[0082] With reference to FIG. 5F, a chemical mechanical polishingprocess as a planarization process is carried out to the firstinter-layer insulator 110, whereby a top surface of the firstinter-layer insulator 110 is planarized. In this chemical mechanicalpolishing process, the top of the gate structure 125 is still buried inthe first inter-layer insulator 110. The chemical mechanical polishingprocess is continued at a calculated time which is calculated from theetching rate. It is unnecessary to check or detect the terminating pointof the chemical mechanical polishing process.

[0083] With reference to FIG. 5G, a first wet etching process is carriedout for etching-back the first inter-layer insulator 110 and the gatestructure 125 with the side wall oxide films 109, so that at least thetop portion of the amorphous silicon dummy layer 122 is shown orprojected, wherein the amorphous silicon dummy layer 122 is lower inetching rate than the first inter-layer insulator 110 and the side walloxide films 109. By this first wet etching process, the anti-reflectivelayer 123 is removed.

[0084] With reference to FIG. 5H, a dry etching process is carried outfor removing the amorphous silicon dummy layer 122 by utilizing adifference in etching selectivity. As a result, the top surface of thesilicon oxide film 121 over the polycrystalline silicon floating gateelectrode layer 106 is shown.

[0085] With reference to FIG. 5I, a second wet etching process iscarried out for etching-back the first inter-layer insulator 110, thesilicon oxide film 121 and the side wall oxide films 109, so that thesilicon oxide film 121 is removed and the planarized top surfaces of thefirst inter-layer insulator 110 and the side wall oxide films 109 areleveled to the top surface of the polycrystalline silicon floating gateelectrode layer 106 by utilizing the difference in the etchingselectivity between the silicon oxide film 121 and the first inter-layerinsulator 110 and the side wall oxide films 109.

[0086] With reference to FIG. 5J, a second polycrystalline silicon film107 having a thickness of about 1000 angstroms or less is entirelyformed over the planarized top surfaces of the first inter-layerinsulator 110, the side wall oxide films 109 and the polycrystallinesilicon floating gate electrode layer 106. The second polycrystallinesilicon film 107 is then patterned to form a polycrystalline siliconcapacitive electrode layer 107. The polycrystalline silicon capacitiveelectrode layer 107 has a width sufficiently covering thepolycrystalline silicon floating gate electrode layer 106. Thepolycrystalline silicon capacitive electrode layer 107 extends along thecolumn direction perpendicular to the width direction. Thepolycrystalline silicon capacitive electrode layer 107 has a rowdirection size of about 0.7 micrometers.

[0087] With reference to FIG. 5K, an ONO inter-gate insulator 108 isentirely formed on the polycrystalline silicon capacitive electrodelayer 107 and the first inter-layer insulator 110. The ONO inter-gateinsulator 108 comprises laminations of an oxide film, a nitride film andan oxide film.

[0088] With reference to FIG. 5L, a third polycrystalline silicon film111 having a thickness of about 1000 angstroms or more is entirelyformed on the ONO inter-gate insulator 108. Laminations of the thirdpolycrystalline silicon film 111, the ONO inter-gate insulator 108, thepolycrystalline silicon capacitive electrode layer 107 and thepolycrystalline silicon floating gate electrode layer 106 areselectively etched or patterned to have the laminations extend in therow direction. The third polycrystalline silicon film 111 and the ONOinter-gate insulator 108 have a column direction size of 0.22micrometers. The adjacent two of the third polycrystalline silicon films111 and the inter-gate insulators 108 have a column directional distanceof 0.22 micrometers. The array of the non-volatile memory cellscomprising the floating gate MOS field effect transistors are formed,wherein the non-volatile memory cells are aligned at a row directionaldistance of 0.68 micrometers and at a column directional distance of0.44 micrometers. Each of the floating gate MOS field effect transistorsas the non-volatile memory cells has a gate length of 0.22 micrometers.

[0089] As described above, the etching selectivity of the amorphoussilicon dummy layer 122 to the resist pattern 124 is in the range of1-2. The etching selectivity of the nitride layer to the resist pattern124 is 0.56. Namely, the amorphous silicon dummy layer 122 is larger inetching selectivity to the resist pattern 124 than the nitride layer,for which reason opposite side edges of the resist film 124 are notover-etched, whereby a horizontal size of the resist film 124 remainsunchanged from the designed size, even after the above gate structure125 is completely defined by this etching process. The over-etching-freeand size-reduction-free resist film 124 makes the amorphous silicondummy layer 122 free from any over-etching in horizontal direction andremain unchanged in horizontal size, whereby the amorphous silicon dummylayer 122 remains unchanged in horizontal size, so that the horizontalsize of the amorphous silicon dummy layer 122 is constant in thevertical direction or the thickness direction. Namely, the side walls ofthe amorphous silicon dummy layer 122 are just vertical. The crosssectional vertical shape of the amorphous silicon dummy layer 122 isrectangle. The over-etching-free and size-reduction-free resist film 124further causes the silicon oxide film 121 and the polycrystallinesilicon floating gate electrode layer 106 to be free from anyover-etching in horizontal direction and to remain unchanged inhorizontal size. The above horizontal size unchanges of the amorphoussilicon dummy layer 122, the silicon oxide film 121 and thepolycrystalline silicon floating gate electrode layer 106 means that thegate structure 125 remains unchanged in horizontal size. This means thatthe gate structure 125 remains unchanged in size in the gate lengthdirection. The n⁻-type lightly doped diffusion regions 104 areself-aligned to the edges of the gate structure 125. No variation insize in the gate length direction of the gate structure 125 causes novariation in position of the inner edges of the n⁻-type lightly dopeddiffusion regions 104, whereby a channel length defined between theinner edges of the n⁻-type lightly doped diffusion regions 104 remainsunchanged. No variation in channel length causes no variations incharacteristics and performances of the memory cells, for example, thenecessary times of writing and erasing data, and ON-current for readingout data. This makes it possible to realize advanced memory cells having0.22 micrometers gate length.

[0090] The amorphous silicon dummy layer 122 is used as the dummy layerfor realizing the highly accurate plane size particularly in the gatelength directional size of the polycrystalline silicon floating gateelectrode layer 106. It is, therefore, impossible to utilize theconventional technique for detecting the polishing termination point inthe chemical mechanical polishing process on the basis of the etchingselectivity between the nitride film and the first inter-layer insulator110 of boro-phospho-silicate glass. In accordance with the presentinvention, therefore, the chemical mechanical polishing process isstopped at the time when the top of the gate structure 125 is stillburied within the first inter-layer insulator 110. This timing ofstopping the chemical mechanical polishing process is decided dependingupon the time. The first wet etching process is carried out foretching-back the first inter-layer insulator 110 and the gate structure125 with the side wall oxide films 109, so that at least the top portionof the amorphous silicon dummy layer 122 is selectively shown orprojected, because the amorphous silicon dummy layer 122 is lower inetching rate than the first inter-layer insulator 110 and the side walloxide films 109. The dry etching process is carried out for removing theamorphous silicon dummy layer 122 by utilizing a difference in etchingselectivity. Further, the second wet etching process is carried out foretching-back the first inter-layer insulator 110, the silicon oxide film121 and the side wall oxide films 109, so that the silicon oxide film121 is removed and the planarized top surfaces of the first inter-layerinsulator 110 and the side wall oxide films 109 are leveled to the topsurface of the polycrystalline silicon floating gate electrode layer 106by utilizing the difference in the etching selectivity between thesilicon oxide film 121 and the first inter-layer insulator 110 and theside wall oxide films 109. Namely, it is possible both that the highlyaccurate plane size particularly in the gate length directional size ofthe polycrystalline silicon floating gate electrode layer 106 isrealized and that the planarized top surfaces of the first inter-layerinsulator 110 and the side wall oxide films 109 are leveled to the topsurface of the polycrystalline silicon floating gate electrode layer106. No variation in size in the gate length direction of the gatestructure 125 causes no variation in position of the inner edges of then⁻-type lightly doped diffusion regions 104, whereby a channel lengthdefined between the inner edges of the n⁻-type lightly doped diffusionregions 104 remains unchanged. No variation in channel length causes novariations in characteristics and performances of the memory cells, forexample, the necessary times of writing and erasing data, and ON-currentfor reading out data. This makes it possible to realize advanced memorycells having 0.22 micrometers gate length.

[0091] In accordance with the present invention, it is also possiblethat the polycrystalline silicon floating gate electrode layer 106 andthe amorphous silicon dummy layer 122 are etched in the same chamber forsimplifying the fabrication processes. By contrast, in accordance withthe conventional technique, it is necessary that the dummy layer made ofnitride and the polycrystalline silicon floating gate electrode layerare etched in the different etching chambers.

[0092] As a first modification to the above first preferred embodimentof the present invention, it is possible that in place of the amorphoussilicon dummy layer 122, the dummy layer may be made of polycrystallinesilicon. The etching selectivity of the polycrystalline silicon dummylayer to the resist pattern is in the range of 1-2. In this case, it isadvantageous that the polycrystalline silicon dummy layer and thepolycrystalline silicon floating gate electrode layer 106 are etched inthe same chamber under the same conditions. Further, the polycrystallinesilicon dummy layer has a crystal structure, for which reason it ispossible that crystal grains are shown on the vertical side walls of thegate structure 125, whereby the vertical side walls of the gatestructure 125 has a surface roughness due to the crystal grains. If theinfluence of the surface roughness due to the crystal grains to the gatelength or the channel length is not so problem, the polycrystallinesilicon dummy layer is suitable. The etching selectivity of thepolycrystalline silicon dummy layer to the resist pattern 124 is in therange of 1-2. The etching selectivity of the nitride layer to the resistpattern 124 is 0.56. Namely, the polycrystalline silicon dummy layer islarger in etching selectivity to the resist pattern 124 than the nitridelayer, for which reason opposite side edges of the resist film 124 arenot over-etched, whereby a horizontal size of the resist film 124remains unchanged from the designed size, even after the above gatestructure 125 is completely defined by this etching process. Theover-etching-free and size-reduction-free resist film 124 makes thepolycrystalline silicon dummy layer free from any over-etching inhorizontal direction and remain unchanged in horizontal size, wherebythe polycrystalline silicon dummy layer remains unchanged in horizontalsize, so that the horizontal size of the polycrystalline silicon dummylayer is constant in the vertical direction or the thickness direction.Namely, the side walls of the polycrystalline silicon dummy layer arejust vertical. The cross sectional vertical shape of the polycrystallinesilicon dummy layer is rectangle. The over-etching-free andsize-reduction-free resist film 124 further causes the silicon oxidefilm 121 and the polycrystalline silicon floating gate electrode layer106 to be free from any over-etching in horizontal direction and toremain unchanged in horizontal size. The above horizontal size unchangesof the polycrystalline silicon dummy layer, the silicon oxide film 121and the polycrystalline silicon floating gate electrode layer 106 meansthat the gate structure 125 remains unchanged in horizontal size. Thismeans that the gate structure 125 remains unchanged in size in the gatelength direction. The n⁻-type lightly doped diffusion regions 104 areself-aligned to the edges of the gate structure 125. No variation insize in the gate length direction of the gate-structure 125 causes novariation in position of the inner edges of the n⁻-type lightly dopeddiffusion regions 104, whereby a channel length defined between theinner edges of the n⁻-type lightly doped diffusion regions 104 remainsunchanged. No variation in channel length causes no variations incharacteristics and performances of the memory cells, for example, thenecessary times of writing and erasing data, and ON-current for readingout data. This makes it possible to realize advanced memory cells having0.22 micrometers gate length.

[0093] As a second modification to the above first preferred embodimentof the present invention, it is possible that in place of the amorphoussilicon dummy layer 122, the dummy layer may be made of CVD oxide. Theetching selectivity of the CVD oxide dummy layer to the resist patternis about 0.7. The etching selectivity of the nitride layer to the resistpattern 124 is 0.56. Namely, the CVD oxide dummy layer is larger inetching selectivity to the resist pattern 124 than the nitride layer,for which reason opposite side edges of the resist film 124 are notover-etched, whereby a horizontal size of the resist film 124 remainsunchanged from the designed size, even after the above gate structure125 is completely defined by this etching process. The over-etching-freeand size-reduction-free resist film 124 makes the CVD oxide dummy layerfree from any over-etching in horizontal direction and remain unchangedin horizontal size, whereby the CVD oxide dummy layer remains unchangedin horizontal size, so that the horizontal size of the CVD oxide dummylayer is constant in the vertical direction or the thickness direction.Namely, the side walls of the CVD oxide dummy layer are just vertical.The cross sectional vertical shape of the CVD oxide dummy layer isrectangle. The over-etching-free and size-reduction-free resist film 124further causes the silicon oxide film 121 and the polycrystallinesilicon floating gate electrode layer 106 to be free from anyover-etching in horizontal direction and to remain unchanged inhorizontal size. The above horizontal size unchanges of the CVD oxidedummy layer, the silicon oxide film 121 and the polycrystalline siliconfloating gate electrode layer 106 means that the gate structure 125remains unchanged in horizontal size. This means that the gate structure125 remains unchanged in size in the gate length direction. The n⁻-typelightly doped diffusion regions 104 are self-aligned to the edges of thegate structure 125. No variation in size in the gate length direction ofthe gate structure 125 causes no variation in position of the inneredges of the n⁻-type lightly doped diffusion regions 104, whereby achannel length defined between the inner edges of the n⁻-type lightlydoped diffusion regions 104 remains unchanged. No variation in channellength causes no variations in characteristics and performances of thememory cells, for example, the necessary times of writing and erasingdata, and ON-current for reading out data. This makes it possible torealize advanced memory cells having 0.22 micrometers gate length.

[0094] As a third modification to the above first preferred embodimentof the present invention, it is possible that in place of the amorphoussilicon dummy layer 122, the dummy layer may be made of plasma oxide.The etching selectivity of the plasma oxide dummy layer to the resistpattern is about 0.7. The etching selectivity of the nitride layer tothe resist pattern 124 is 0.56. Namely, the plasma oxide dummy layer islarger in etching selectivity to the resist pattern 124 than the nitridelayer, for which reason opposite side edges of the resist film 124 arenot over-etched, whereby a horizontal size of the resist film 124remains unchanged from the designed size, even after the above gatestructure 125 is completely defined by this etching process. Theover-etching-free and size-reduction-free resist film 124 makes theplasma oxide dummy layer free from any over-etching in horizontaldirection and remain unchanged in horizontal size, whereby the plasmaoxide dummy layer remains unchanged in horizontal size, so that thehorizontal size of the plasma oxide dummy layer is constant in thevertical direction or the thickness direction. Namely, the side walls ofthe plasma oxide dummy layer are just vertical. The cross sectionalvertical shape of the plasma oxide dummy layer is rectangle. Theover-etching-free and size-reduction-free resist film 124 further causesthe silicon oxide film 121 and the polycrystalline silicon floating gateelectrode layer 106 to be free from any over-etching in horizontaldirection and to remain unchanged in horizontal size. The abovehorizontal size unchanges of the plasma oxide dummy layer, the siliconoxide film 121 and the polycrystalline silicon floating gate electrodelayer 106 means that the gate structure 125 remains unchanged inhorizontal size. This means that the gate structure 125 remainsunchanged in size in the gate length direction. The n⁻-type lightlydoped diffusion regions 104 are self-aligned to the edges of the gatestructure 125. No variation in size in the gate length direction of thegate structure 125 causes no variation in position of the inner edges ofthe n⁻-type lightly doped diffusion regions 104, whereby a channellength defined between the inner edges of the n⁻-type lightly dopeddiffusion regions 104 remains unchanged. No variation in channel lengthcauses no variations in characteristics and performances of the memorycells, for example, the necessary times of writing and erasing data, andON-current for reading out data. This makes it possible to realizeadvanced memory cells having 0.22 micrometers gate length.

[0095] As a fourth modification to the above first preferred embodimentof the present invention, it is possible that in place of the amorphoussilicon dummy layer 122, the dummy layer may be made ofboro-phospho-silicate-glass. The etching selectivity of theboro-phospho-silicate-glass dummy layer to the resist pattern is about0.7. The etching selectivity of the nitride layer to the resist pattern124 is 0.56. Namely, the boro-phospho-silicate-glass dummy layer islarger in etching selectivity to the resist pattern 124 than the nitridelayer, for which reason opposite side edges of the resist film 124 arenot over-etched, whereby a horizontal size of the resist film 124remains unchanged from the designed size, even after the above gatestructure 125 is completely defined by this etching process. Theover-etching-free and size-reduction-free resist film 124 makes theboro-phospho-silicate-glass dummy layer free from any over-etching inhorizontal direction and remain unchanged in horizontal size, wherebythe boro-phospho-silicate-glass dummy layer remains unchanged inhorizontal size, so that the horizontal size of theboro-phospho-silicate-glass dummy layer is constant in the verticaldirection or the thickness direction. Namely, the side walls of theboro-phospho-silicate-glass dummy layer are just vertical. The crosssectional vertical shape of the boro-phospho-silicate-glass dummy layeris rectangle. The over-etching-free and size-reduction-free resist film124 further causes the silicon oxide film 121 and the polycrystallinesilicon floating gate electrode layer 106 to be free from anyover-etching in horizontal direction and to remain unchanged inhorizontal size. The above horizontal size unchanges of theboro-phospho-silicate-glass dummy layer, the silicon oxide film 121 andthe polycrystalline silicon floating gate electrode layer 106 means thatthe gate structure 125 remains unchanged in horizontal size. This meansthat the gate structure 125 remains unchanged in size in the gate lengthdirection. The n⁻-type lightly doped diffusion regions 104 areself-aligned to the edges of the gate structure 125. No variation insize in the gate length direction of the gate structure 125 causes novariation in position of the inner edges of the n⁻-type lightly dopeddiffusion regions 104, whereby a channel length defined between theinner edges of the n⁻-type lightly doped diffusion regions 104 remainsunchanged. No variation in channel length causes no variations incharacteristics and performances of the memory cells, for example, thenecessary times of writing and erasing data, and ON-current for readingout data. This makes it possible to realize advanced memory cells having0.22 micrometers gate length.

[0096] As a fifth modification to the above first preferred embodimentof the present invention, it is possible that in place of the amorphoussilicon dummy layer 122, the dummy layer may be made of polycrystallinesilicon and further in place of the polycrystalline silicon floatinggate electrode layer 106, an amorphous silicon floating gate electrodelayer is used. In this case, it is advantageous that the amorphoussilicon dummy layer and the amorphous silicon floating gate electrodelayer are etched in the same chamber under the same conditions.

[0097]FIG. 6 is a fragmentary cross sectional elevation viewillustrative of a semiconductor device having a memory cell area and aperipheral circuit area. The above novel memory cell arrays are formedin the memory cell area which is surrounded by the peripheral circuitarea. MOS field effect transistors having large gate lengths are formedin the peripheral circuit area in the same processes as in the processesfor forming the memory cells. In the above chemical mechanical polishingprocess shown in FIG. 5F, the volume of the first inter-layer insulator110 in the peripheral circuit area is much larger than the volume of thefirst inter-layer insulator 110 in the memory cell area. This may makeit difficult to realize a highly accurate planarization of the firstinter-layer insulator 110 by the chemical mechanical polishing process.In this case, it is effective for realizing the highly accurateplanarization of the first inter-layer insulator 110 that after thefirst inter-layer insulator 110 has been formed, then a selectiveetching is carried out for selectively etching the first inter-layerinsulator 110 but only on the peripheral circuit area by a predeterminedthickness, before a thin silicon nitride film not illustrated isentirely formed on the first inter-layer insulator 110 over the memorycell area and the peripheral circuit area, prior to the chemicalmechanical polishing process is carried out to the first inter-layerinsulator 110 over the memory cell area and the peripheral circuit area.This makes it possible to realize the highly accurate planarization ofthe first inter-layer insulator 110 over the memory cell area and theperipheral circuit area.

[0098] Alternatively, it is also effective for realizing the highlyaccurate planarization of the first inter-layer insulator 110 that afterthe first inter-layer insulator 110 has been formed, then a thin siliconnitride film not illustrated is entirely formed on the first inter-layerinsulator 110 over the memory cell area and the peripheral circuit area,before a selective etching is carried out for selectively etching thefirst inter-layer insulator 110 but only on the peripheral circuit areaby a predetermined thickness, prior to the chemical mechanical polishingprocess is carried out to the first inter-layer insulator 110 over thememory cell area and the peripheral circuit area. This makes it possibleto realize the highly accurate planarization of the first inter-layerinsulator 110 over the memory cell area and the peripheral circuit area.

[0099] Whereas modifications of the present invention will be apparentto a person having ordinary skill in the art, to which the inventionpertains, it is to be understood that embodiments as shown and describedby way of illustrations are by no means intended to be considered in alimiting sense. Accordingly, it is to be intended to cover by claims allmodifications which fall within the spirit and scope of the presentinvention.

What is claimed is:
 1. A dummy layer pattern provided over a conductivelayer pattern buried in an inter-layer insulator for protecting saidconductive layer pattern from being over-polished by a chemicalmechanical polishing process, wherein said dummy layer pattern has ahigher etching selectivity to said inter-layer insulator than nitride.2. The dummy layer pattern as claimed in claim 1, wherein said dummylayer pattern comprises an amorphous silicon layer.
 3. The dummy layerpattern as claimed in claim 1, wherein said dummy layer patterncomprises a polycrystalline silicon layer.
 4. The dummy layer pattern asclaimed in claim 1, wherein said dummy layer pattern comprises a CVDoxide layer.
 5. The method as claimed in claim 1, wherein said dummylayer dummy layer pattern a plasma enhanced silicon oxide layer.
 6. Themethod as claimed in claim 1, wherein said dummy layer dummy layerpattern a boro-phospho-silicate glass layer.